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Mapping homogeneous computations onto dynamically configurable coarse-grained architectures

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2 Author(s)
A. Dandalis ; Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA ; V. K. Prasanna

FPGAs are fine-grained architectures, mainly designed for implementing bit-level tasks and random logic functions. Their performance is limited for computationally demanding applications over large word length data. A highly promising avenue that is being explored by many research groups is coarse-grained configurable architectures. These architectures are datapath-oriented structures and consist of a small number of powerful, word-based configurable processing elements (PEs). Such architectures can result in greater computational efficiency and high throughput for coarse-grained computing tasks. The key for achieving high performance solutions is efficient mapping of tasks onto above architectures. In addition to achieving high computational rates, partitionability is a desirable characteristic of the mapping. Moreover, the computational efficiency must scale with the size of the architecture. Finally, it must result in a simple PE structure, regular/balanced dataflow and sustainable I/O requirements so that it can be realized in hardware. In this paper we show a methodology for deriving dynamic computation structures for 2 dimensioned homogeneous computations. Homogeneous computations lead to all PEs having the same functionality. The derived dynamic structures match the datapath-oriented nature of coarse-grained architectures and lead to efficient mapping schemes. Our solutions require constant I/O and smaller amount of local memory/PE compared with known solutions

Published in:

FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on

Date of Conference:

15-17 Apr 1998