Scalable network based FPGA accelerators for an automatic target recognition application

Image processing, specifically automatic target recognition (ATR) in synthetic aperture radar (SAR) imagery, is an application area that can require tremendous processing throughput. In this application, data comes from high bandwidth sensors, where the processing is time-critical. There is limited space and power for processing the data in the sensor platforms or in battlefield groundstations. DoD's strong push for using commercial-off-the-shelf (COTS) technology, the very high non-recurring engineering (NRE) costs for low volume ASICs, and evolving algorithms limit the feasibility of using custom special purpose hardware. In addition, a scalable system is required as the different sensor platforms have different image pixel rates and different mission requirements have different target recognition throughput needs per pixel. In this paper, we describe an ATR algorithm implementation using FPGA accelerators. We first describe the ATR algorithm that was implemented, the implementation on a single FPGA, how the FPGA nodes are connected to make a scalable system, and compare the performance to current scalable microprocessor-based implementations.