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An architecture simulator for National Semiconductor's adaptive processing architecture (NAPA)

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Early simulation is a very important tool in the development any large scale system. Accuracy and flexibility are critical characteristics which allow the architect to explore the design tradeoff space. Moreover, in many systems, especially those for reconfigurable computing, a good simulation environment will continue to be used long after the architecture solidifies, serving a variety of roles including as a platform for the development of run time systems, programming tools, benchmarks, and even end applications. Therefore, visibility, controllability and user interface are also important design considerations. National Semiconductor's Adaptive Processing Architecture (NAPA) integrates a Fixed Instruction set Processor (FIP), an Adaptive Logic Processor (ALP), memory and other support circuitry into a single reconfigurable computing device. The NAPA architecture simulator, NAPAsim, consists of a C language, cycle accurate model of the RISC core, peripherals and memories, coupled with an event driven logic simulator for modelling the user-defined contents of the reconfigurable logic and a Tcl/Tk based GUI to provide source level symbolic debugging capabilities. NAPAsim was developed to serve as both a tool for architectural exploration and as a platform for system and application software development

Published in:

FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on

Date of Conference:

15-17 Apr 1998