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A reconfigurable multiplier array for video image processing tasks, suitable for embedding in an FPGA structure

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2 Author(s)
Haynes, S.D. ; Dept. of Electr. & Electron. Eng., Imperial Coll. of Sci., Technol. & Med., London, UK ; Cheung, P.Y.K.

This paper presents a design for a reconfigurable multiplier array. The multiplier is constructed using an array of 4 bit Flexible Array Blocks (FABs), which could be embedded within a conventional FPGA structure. The array can be configured to perform a number of 4n×4m bit signed/unsigned binary multiplications. We have estimated that the FABs are about 25 times more efficient in area than the equivalent multiplier implemented using a conventional FPGA structure alone

Published in:

FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on

Date of Conference:

15-17 Apr 1998

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