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A variable long-precision arithmetic unit design for reconfigurable coprocessor architectures

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2 Author(s)
A. F. Tenca ; Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA ; M. D. Ercegovac

This paper presents the organization of an arithmetic unit for variable long-precision (VLP) operands suitable for reconfigurable computing. The reconfigurable arithmetic coprocessor (RAC) cooperates with the host computer in the VLP tasks. The main design issues addressed in the paper are: (a) mapping of the most frequent and time consuming operations of the VLP arithmetic algorithms to RAG, and (b) design of VLP algorithms that allow reduced reconfiguration time between arithmetic operations. The VLP arithmetic algorithms proposed cover multiplication, division and square root. In this paper we present the main building blocks used in the VLP arithmetic circuits, show the similarities of each arithmetic operator and present area/time estimates of these circuits in Xilinx FPGAs

Published in:

FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on

Date of Conference:

15-17 Apr 1998