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Configuration compression for the Xilinx XC6200 FPGA

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3 Author(s)
S. Hauck ; Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA ; Zhiyuan Li ; E. Schwabe

One of the major overheads in reconfigurable computing is the time it takes to reconfigure the devices in the system. This overhead limits the speedups possible in this exciting new paradigm. In this paper we explore one technique for reducing this overhead: the compression of configuration datastreams. We develop an algorithm, targeted to the decompression hardware imbedded in the Xilinx XC6200 series FPGA architecture, that can radically reduce the amount of data needed to transfer during reconfiguration. This results in an overall reduction of almost 4 in total bandwidth required for reconfiguration

Published in:

FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on

Date of Conference:

15-17 Apr 1998