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Competitive learning algorithms and neurocomputer architecture

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4 Author(s)
Card, H.C. ; Dept. of Electr. & Comput. Eng., Manitoba Univ., Winnipeg, Man., Canada ; Rosendahl, G.K. ; McNeill, D.K. ; McLeod, R.D.

This paper begins with an overview of several competitive learning algorithms in artificial neural networks, including self-organizing feature maps, focusing on properties of these algorithms important to hardware implementations. We then discuss previously reported digital implementations of these networks. Finally, we report a reconfigurable parallel neurocomputer architecture we have designed using digital signal processing chips and field-programmable gate array devices. Communications are based upon a broadcast network with FPGA-based message preprocessing and postprocessing. A small prototype of this system has been constructed and applied to competitive learning in self-organizing maps. This machine is able to model slowly-varying nonstationary data in real time

Published in:

Computers, IEEE Transactions on  (Volume:47 ,  Issue: 8 )

Date of Publication:

Aug 1998

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