A /spl plusmn/1.5 V CMOS four-quadrant analogue multiplier using 3 GHz analogue squaring circuits

A CMOS four-quadrant analog multiplier using the MOS transistors operated in triode region is proposed. The multiplier is basically constructed by voltage substractors for two differential inputs, and two 3 GHz analog squarers for multiplication. Simulation results are given to verify the theoretical analysis. The multiplier has a nonlinearity error less than 1% over /spl plusmn/1.5 V input range. The circuit provides a -3 dB bandwidth higher than 1.2 GHz and exhibits a THD lower than 4% with a 1.5 V peak-to-peak input voltage, which dissipating 249 /spl mu/W. The second-order effects including mismatch effects are discussed. The proposed circuit will be useful in analog RF signal-processing applications.