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A ±1.5 V CMOS four-quadrant analogue multiplier using 3 GHz analogue squaring circuits

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2 Author(s)
Li, S.C. ; Adv. Technol. & Integrated Lab., Nat. Yunlin Univ. of Sci. & Technol., Taiwan, China ; Kaung-Long Lin

A CMOS four-quadrant analog multiplier using the MOS transistors operated in triode region is proposed. The multiplier is basically constructed by voltage substractors for two differential inputs, and two 3 GHz analog squarers for multiplication. Simulation results are given to verify the theoretical analysis. The multiplier has a nonlinearity error less than 1% over ±1.5 V input range. The circuit provides a -3 dB bandwidth higher than 1.2 GHz and exhibits a THD lower than 4% with a 1.5 V peak-to-peak input voltage, which dissipating 249 μW. The second-order effects including mismatch effects are discussed. The proposed circuit will be useful in analog RF signal-processing applications

Published in:

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on  (Volume:2 )

Date of Conference:

31 May-3 Jun 1998