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General data-path organization of a MAC unit for VLSI implementation of DSP processors

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2 Author(s)
Farooqui, A.A. ; Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA ; Oklobdzija, V.G.

This paper describes the data-path and VLSI implementation of a 32×32 bit signed/unsigned multiply accumulate (MAC) unit. In this design we have solved the problem of dealing with signed and unsigned numbers simultaneously, using the modified Booth algorithm. This MAC unit can perform 32×32, 32×16, and two 16×16 multiplications, on signed/unsigned operands with a throughput of 2,1, and 1 cycle, respectively. The Booth encoding technique reduces the number of partial products (PP) by half. Further increase in speed is achieved by using the Three Dimensional reduction Method (TDM) to add the partial products. Special circuitry has been designed to accommodate sign/unsigned operands and to deal with sign extension. The modified Booth algorithm coupled with TDM and sign correction circuitry results in a multiplier, with a delay (partial product addition) equivalent to 6 XOR gates. The MAC unit has been modeled in VHDL, and it implements an algorithm which makes this data path organization fast and efficient in silicon

Published in:

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on  (Volume:2 )

Date of Conference:

31 May-3 Jun 1998