By Topic

An interconnect transient coupling induced noise susceptibility for dynamic circuits in deep submicron CMOS technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Lee, M. ; Digital Compression Products, Texas Instrum. Inc., Dallas, TX, USA ; Darley, M.H.

This paper investigates the susceptibility of Dynamic Logic (DL) noises which are induced during interconnect coupling signal disturbances. We describe transient current/voltage coupling behaviors for a DL noise analysis in terms of far-end crosstalk peak voltage (ΔVcr) and DL's weak node noise voltage dip (ΔV dn) as a function of pull down transistor threshold voltage (Vt) and signal input slew rate (S). The worst case interconnect arrays are modeled with accurate parasitic RLC elements extracted by 3D field solver and are connected to either high Vt and/or low Vt pull down transistor for DL's noise margin simulations. We fully investigate the impacts of driving signal's pull up/down transistor strength, duty cycle, and different operating conditions on transient crosstalk waveforms

Published in:

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on  (Volume:2 )

Date of Conference:

31 May-3 Jun 1998