An interconnect transient coupling induced noise susceptibility for dynamic circuits in deep submicron CMOS technology

This paper investigates the susceptibility of Dynamic Logic (DL) noises which are induced during interconnect coupling signal disturbances. We describe transient current/voltage coupling behaviors for a DL noise analysis in terms of far-end crosstalk peak voltage (/spl Delta/V/sub cr/) and DL's weak node noise voltage dip (/spl Delta/V/sub dn/) as a function of pull down transistor threshold voltage (V/sub t/) and signal input slew rate (S). The worst case interconnect arrays are modeled with accurate parasitic RLC elements extracted by 3D field solver and are connected to either high V/sub t/ and/or low V/sub t/ pull down transistor for DL's noise margin simulations. We fully investigate the impacts of driving signal's pull up/down transistor strength, duty cycle, and different operating conditions on transient crosstalk waveforms.