By Topic

Interconnect inductance effects on delay and crosstalk for long on-chip nets with fast input slew rates

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
M. Lee ; Digital Compression Products, Texas Instrum. Inc., Dallas, TX, USA ; A. Hill ; M. H. Darley

In this paper, we address the significance of parasitic inductance on designing signal coupling shields and clock tree distributions in terms of input slew rate and interconnect length by using 3D RLC parasitic extraction and Spice simulation for 500 MHz clocks and 0.15 μm process interconnect technology. We report a larger crosstalk deviation under fast input slew rates and a higher clock skew variation due to wiring inductive effect for low resistive long nets which should be considered for future high-speed design. In addition, we propose a feasible one-level interleaved clock shielding scheme with optimized dimensions for a minimal clock skew and compare it to a worst case signal coupling three-level clock shielding scheme

Published in:

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on  (Volume:2 )

Date of Conference:

31 May-3 Jun 1998