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A scalable shared buffer ATM switch embedded SPRAMS

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4 Author(s)
Gab Joong Jeong ; Dept. of Electr. Eng., Yonsei Univ., Seoul, South Korea ; Jae Wook Shim ; Moon Key Lee ; Seung Han Ahn

This paper describes the architecture of a scalable shared buffer ATM switch and VLSI implementation. It provides scalability in port size and buffer size. The prototype chip has been designed for 4×4 ATM switch which has a shared buffer for 128 ATM cells. It is integrated in 0.6 μm twin well, double-metal, and single-poly CMOS technology. Operating frequency is 80 MHz. Core size is 11×10 mm2. It supports 622 Mbps per port

Published in:

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on  (Volume:2 )

Date of Conference:

31 May-3 Jun 1998