Tutorial on DRAM fault modeling and test pattern design

Summary form only given, as follows. The problem of designing efficient and effective tests for semiconductor memories poses a daunting challenge to the test engineer. As commodity memory capacities approach the 1 Gb level by the end of this decade, testing cost becomes the largest component of the total cost of production. It is therefore essential to understand the precise nature of memory defects and failure mechanisms and to therefore be in the best position to design the most economic tests. A further complication in recent years has been the proliferation of specialized memory technologies, configurations and data access modes. This tutorial presentation focuses on reviewing the important fundamental concepts and techniques that are required to design high-quality tests for testing the cell arrays of dynamic random-access memories. Much of the memory testing literature has considered rather abstract functional fault models that appear to have little obvious justification in terms of observed faulty behaviors. In particular, much of the literature has dealt with fault models that would seem more appropriate for testing static rather than dynamic memory. The much larger production volume of DRAMs compared to that of SRAMs justifies specialized DRAM test methods. The topics covered in this presentation include the following: a brief review of DRAM architecture and operation; DRAM-specific defects and failure mechanisms; sources of soft failures and array noise; DRAM-specific fault models; the design of tests for the cell array; tests for fault location and diagnosis; and recommended tests for embedded DRAMs.