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Integration of multi-level copper metallization into a high performance sub-0.25 μm CMOS technology

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28 Author(s)
S. Venkatesan ; Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA ; R. Venkatraman ; A. Jain ; J. Mendonca
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A high performance sub-0.25 μm CMOS technology has been developed with six levels of planarized copper interconnects. 0.15 μm transistors (Lgate=0.15 μm) are optimized for 1.8 V operation to provide high performance with low power-delay products and excellent reliability. Copper has been integrated into the back-end to provide low resistance interconnects to minimize wiring induced RC delays

Published in:

Devices, Circuits and Systems, 1998. Proceedings of the 1998 Second IEEE International Caracas Conference on

Date of Conference:

2-4 Mar 1998