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Hardware-efficient systolic architecture for inversion and division in GF(2m)

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2 Author(s)
J. -H. Guo ; Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; C. -L. Wang

Two parallel-in parallel-out systolic arrays for computing inverses and divisions in finite fields GF(2m) with the standard basis representation are presented. Both architectures realise a new variant of Euclid's algorithm. One of the proposed arrays involves O(m2) area complexity and O(1) time complexity, while the other involves O(m) area complexity and O(m) time complexity. They are highly regular, modular and thus well suited to VLSI implementation. Compared to existing related systolic architectures with the same time complexity, our proposed arrays involve less chip area and smaller latency. It should be noted that, to perform inversion only, both the proposed arrays can be simplified

Published in:

IEE Proceedings - Computers and Digital Techniques  (Volume:145 ,  Issue: 4 )