By Topic

Hardware-efficient systolic architecture for inversion and division in GF(2m)

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Guo, J.-H. ; Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Wang, C.-L.

Two parallel-in parallel-out systolic arrays for computing inverses and divisions in finite fields GF(2m) with the standard basis representation are presented. Both architectures realise a new variant of Euclid's algorithm. One of the proposed arrays involves O(m2) area complexity and O(1) time complexity, while the other involves O(m) area complexity and O(m) time complexity. They are highly regular, modular and thus well suited to VLSI implementation. Compared to existing related systolic architectures with the same time complexity, our proposed arrays involve less chip area and smaller latency. It should be noted that, to perform inversion only, both the proposed arrays can be simplified

Published in:

Computers and Digital Techniques, IEE Proceedings -  (Volume:145 ,  Issue: 4 )