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A step-down boosted-wordline scheme for 1-V battery-operated fast SRAM's

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2 Author(s)
Morimura, H. ; Integrated Inf. & Energy Syst. Labs., NTT, Kanagawa, Japan ; Shibata, N.

Fast and low-power circuit techniques for battery-operated low-voltage SRAM's are described. To shorten the read access time with low power dissipation, the step-down boosted-wordline scheme, which is combined with current-sense amplifiers, is proposed. Boosting a selected-wordline voltage shortens the bitline delay before the stored data are sensed. The power dissipation while selecting a wordline is suppressed by stepping down the selected-wordline potential. Moreover, to reduce the standby power, a switched-capacitor-type boosted-pulse generator, which is controlled by an address transition detection (ATD) signal, is used. A 61 kword×16-bit organization SRAM test chip was fabricated using the 0.5-μm multithreshold-voltage CMOS (MTCMOS) process. The power dissipation in the memory array is reduced to 57% (1 mW) at 10 kHz operation in comparison with the conventional boosted-wordline scheme

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:33 ,  Issue: 8 )