Referenced Items are not available for this document.
Fast and low-power circuit techniques for battery-operated low-voltage SRAM's are described. To shorten the read access time with low power dissipation, the step-down boosted-wordline scheme, which is combined with current-sense amplifiers, is proposed. Boosting a selected-wordline voltage shortens the bitline delay before the stored data are sensed. The power dissipation while selecting a wordline is suppressed by stepping down the selected-wordline potential. Moreover, to reduce the standby power, a switched-capacitor-type boosted-pulse generator, which is controlled by an address transition detection (ATD) signal, is used. A 61 kword×16-bit organization SRAM test chip was fabricated using the 0.5-μm multithreshold-voltage CMOS (MTCMOS) process. The power dissipation in the memory array is reduced to 57% (1 mW) at 10 kHz operation in comparison with the conventional boosted-wordline scheme
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:33
,
Issue:
8
)
Date of Publication: Aug 1998
- Page(s):
- 1220 - 1227
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 6007874
- Digital Object Identifier :
- 10.1109/4.705360
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Aug 1998
- Sponsored by :
- IEEE Solid-State Circuits Society
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