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A new memory controller for the shared multibuffer ATM switch with multicast functions

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2 Author(s)
Chang, R.C. ; Dept. of Electr. Eng., Nat. Chung-Hsing Univ., Taichung, Taiwan ; Chih-Yuan Hsieh

A novel ATM switch memory controller incorporated the shared multibuffer architecture is proposed. By applying the cyclic N method at the address queues, the blocking effect is eliminated and no memory and cross-point switch speed up is required. Multicast functions are efficiently carried out via a multicast queue. Each multicast packet only occupies one space in buffer memory and no additional copy circuit or counter is needed. Thus, the buffer utilization is improved and the hardware complexity is reduced. With the aid of the input traffic adaptive controller, multicast packets are dynamically sent to the output ports according to the input traffic pattern so that the unfairness problem due to employing the multicast queue is alleviated. By adopting the new memory controller, the throughput can be elevated to about 99.2%

Published in:

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on  (Volume:6 )

Date of Conference:

31 May-3 Jun 1998

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