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Two-step current-memory cells with optimal dynamic range for advanced CMOS technologies

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1 Author(s)
Kaiser, A. ; Dept. ISEN, CNRS, Lille, France

Improved two-step current-memory cell architectures employing current conveyors are proposed and compared with conventional ones over a wide range of technologies. Special emphasis is given to the evaluation of performance on very advanced state-of the art CMOS processes and the operation at low supply voltages. Up to 50% power savings can be expected with respect to conventional cells of the same performance

Published in:

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on  (Volume:1 )

Date of Conference:

31 May-3 Jun 1998

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