Referenced Items are not available for this document.
A low-voltage low-power CMOS current-mode pipeline ADC is presented. Zero-voltage sampling technique and regulated cascode circuits are combined in the sample-and-hold circuits to increase the resolution. Dynamic latched-type comparators are used to implement high-speed low-power sub-ADCs. The multiplying DAC and the comparators are used with a digital error correction (DEC) circuit to realize a low-voltage low-power current-mode pipeline ADC. Simulation shows that the ADC can work at 20 MHz with an 8-bit resolution. The power consumption is 22 mW
Published in:
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
(Volume:1
)
Date of Conference: 31 May-3 Jun 1998
- Page(s):
- 9 - 12 vol.1
- Meeting Date :
- 31 May 1998-03 Jun 1998
- Print ISBN:
- 0-7803-4455-3
- INSPEC Accession Number:
- 5992493
- Conference Location :
- Monterey, CA
- Digital Object Identifier :
- 10.1109/ISCAS.1998.704122
- Product Type:
- Conference Publications
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