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LOT: Logic Optimization with Testability. New transformations for logic synthesis

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3 Author(s)
M. Chatterjee ; Design Autom. Group, Integrated Device Technol. Inc., Santa Clara, CA, USA ; D. K. Pradhan ; W. Kunz

A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random pattern testability. The method is based on structural transformations at the gate level. New transformations involving EX-OR gates as well as Reed-Muller expansions have been introduced in the synthesis of multilevel circuits. This method is augmented with transformations that specifically enhance random-pattern testability while reducing the area. Testability enhancement is an integral part of our synthesis methodology. Experimental results show that the proposed methodology not only can achieve lower area than other similar tools, but that it achieves better testability compared to available testability enhancement tools such as tstfx. Specifically for ISCAS-85 benchmark circuits, it was observed that EX-OR gate-based transformations successfully contributed toward generating smaller circuits compared to other state-of-the-art logic optimization tools

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:17 ,  Issue: 5 )