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Address generation for memories containing multiple arrays

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2 Author(s)
H. Schmit ; Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA ; D. E. Thomas

We present techniques for generating addresses for memories containing multiple arrays. Because these techniques rely on the inversion or rearrangement of address bits, they are faster and require less hardware to compute than the traditional technique of addition. Use of these techniques can improve performance and cost of application-specific memory subsystems by decreasing effective access time to arrays and by reducing address generation hardware. The primary drawback to this approach is that extra memory space is occasionally required, but in over a million tested cases, this extra memory space is on average only 2% and no worse than 17.4% of the utilized memory space. This amount of wasted address space is significantly less than the amount required by the only known similar technique and rarely necessitates the allocation of additional memory components. These techniques provide a foundation for adder-free address generation for manually and automatically generated application-specific memory designs

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:17 ,  Issue: 5 )