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Optimal clock period clustering for sequential circuits with retiming

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3 Author(s)
P. Pan ; Dept. of Electr. & Comput. Eng., Clarkson Univ., Potsdam, NY, USA ; A. K. Karandikar ; C. L. Liu

In this paper we consider the problem of clustering sequential circuits subject to a bound on the area of each cluster, with the objective of minimizing the clock period. Current algorithms address combinational circuits only, and treat a sequential circuit as a special case, by removing all flip-flops (FF's) and clustering the combinational part of the sequential circuit. This approach breaks the signal dependencies and assumes the positions of FF's are fixed. The positions of the FF's in a sequential circuit are in fact dynamic, because of retiming. As a result, current algorithms can only consider a small portion of the whole solution space. In this paper, we present a clustering algorithm that does not segment circuits by removing FF's. In additional, it considers the effect of retiming. The algorithm can produce clustering solutions with the optimal clock period under the unit delay model. For the general delay model, it can produce clustering solutions with a clock period provably close to optimal

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:17 ,  Issue: 6 )