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The path-status graph with application to delay fault simulation

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3 Author(s)
Gharaybeh, M.A. ; CAIP Center, Rutgers Univ., Piscataway, NJ, USA ; Bushnell, M.L. ; Agrawal, V.D.

We present an efficient path-delay fault (PDF) simulator that does not involve the enumeration of paths. Our method calculates the exact fault coverage, and identifies all tested faults in any circuit with a large number of paths. We present a new data structure, called the path-status graph (PSG), to efficiently hold the status of each PDF in the circuit, i.e., whether or not the PDF is tested. The keg to this efficiency is in breaking the information into pieces and distributing it over the data structure, and in retaining all or part of the reconverging fan-out structure of the circuit in the PSG. Thus, an exponential number of PDF's can share the same piece of information. Using 1000 random tests, we simulated all of the approximately 1020 PDF's in the circuit c6288, and determined that 4.4 billion faults were detected. This number is larger by over three orders of magnitude compared to what was possible with previously reported methods

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:17 ,  Issue: 4 )