A 20-V p-channel with 650 /spl mu//spl Omega/-cm/sup 2/ at V/sub GS/=2.7 V: Overcoming FPI breakdown in high-channel-conductance low-V/sub t/ trenchFETs

A 5 Mcell/cm/sup 2/ (32 Mcell/in/sup 2/) low-threshold 20-V p-channel trenchFET (U-groove trench-gated DMOSFET) is reported, achieving specific on-resistances of 450, 650 and 720 /spl mu//spl Omega/-cm/sup 2/ at V/sub GS/ biases of 4.5, 2.7 and 2.5 V, respectively. A distributed 1-of-n avalanche voltage clamp is employed to achieve high cell densities and high channel conductance, while mitigating field plate induced (FPI) breakdown associated with scaled (12 V maximum rated) trench gate oxides. The measured on-resistance, which is 60% of that of a prior generation 1.9 Mcell/cm/sup 2/ design, represents the lowest reported p-channel specific on-resistance.