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A 20-V p-channel with 650 μΩ-cm2 at VGS =2.7 V: Overcoming FPI breakdown in high-channel-conductance low-V t trenchFETs

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5 Author(s)
Williams, R.K. ; Siliconix Inc., Santa Clara, CA, USA ; Grabowski, W. ; Berwick, J. ; Darwish, M.
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A 5 Mcell/cm2 (32 Mcell/in2) low-threshold 20-V p-channel trenchFET (U-groove trench-gated DMOSFET) is reported, achieving specific on-resistances of 450, 650 and 720 μΩ-cm2 at VGS biases of 4.5, 2.7 and 2.5 V, respectively. A distributed 1-of-n avalanche voltage clamp is employed to achieve high cell densities and high channel conductance, while mitigating field plate induced (FPI) breakdown associated with scaled (12 V maximum rated) trench gate oxides. The measured on-resistance, which is 60% of that of a prior generation 1.9 Mcell/cm 2 design, represents the lowest reported p-channel specific on-resistance

Published in:

Power Semiconductor Devices and ICs, 1998. ISPSD 98. Proceedings of the 10th International Symposium on

Date of Conference:

3-6 Jun 1998