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High-frequency performances of a partially depleted 0.18-μm SOI/CMOS technology at low supply voltage-influence of parasitic elements

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8 Author(s)
V. Ferlet-Cavrois ; Centre de Bruyeres-le-Chatel, CEA, France ; C. Marcandella ; O. Musseau ; J. L. Leray
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This paper shows for the first time the high-performances of a partially depleted 0.18-μ/sub m/ technology at low supply voltage. The SOI technology uses a standard digital process with a TiSi2 salicided polysilicon gate and a low dose SIMOX substrate. The process does not include any specific feature like T-gate, or high-resistivity SOI substrate. At 1 V, and 2 GHz the current gain and the unilateral power gain are higher than 15 dB for both 0.18 μm gate length NMOS and PMOS transistors. At 1.5 V, the 0.18-μm NMOS and PMOS show a transition frequency of, respectively, 51 GHz and 23 GHz and a maximum oscillation frequency of 28 GHz and 13 GHz. These results have been obtained with an optimized transistor geometry to reduce the influence of the access resistances. The high-frequency potential of this 0.18-μm SOI technology demonstrates the possible integration of microwave functions with digital circuits on a single chip for low-power, low-voltage applications like wireless telecommunication.

Published in:

IEEE Electron Device Letters  (Volume:19 ,  Issue: 7 )