By Topic

A robust analog interface system for submicron CMOS video DSP

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
W. Redman-White ; Philips Semicond., Southampton, UK ; R. Duffee ; S. Bramwell ; H. Rijns
more authors

This paper describes the front-end architecture for a fully integrated low-voltage CMOS video DSP function, including AGC, equalization, clamping, sync, and A/D conversion. With multiple clock domains and many high-activity pads, the large digital section of the IC generates high levels of substrate and power line noise, which cannot be avoided with quiet period sampling. The analog section is therefore designed to minimize the injected noise by other circuit techniques. The system maximizes the available dynamic range in the 3.3-V supply, with several high-bandwidth rail-to-rail functions. A novel arrangement with high noise immunity level estimators is used to clamp the video in the middle of the dynamic range of the input amplifier, hence reducing amplification of unwanted dc components. Extensive mixed signal test facilities are also included in the design. The chip is fabricated in 0.5-μm CMOS, and operates from a single 3.3-V supply

Published in:

IEEE Journal of Solid-State Circuits  (Volume:33 ,  Issue: 7 )