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A 15-b resolution 2-MHz Nyquist rate ΔΣ ADC in a 1-μm CMOS technology

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4 Author(s)
Marques, A.M. ; ESAT, Katholieke Univ., Leuven, Heverlee, Belgium ; Peluso, V. ; Steyaert, M.S.J. ; Sansen, Willy

A high-resolution high-speed fourth-order cascaded ΔΣ analog-to-digital converter, based on a 2-1-1 topology, is presented. The converter is implemented with fully differential switched capacitor circuits in a standard 1-μm CMOS technology. The converter uses two symmetrical reference voltages of 1 V, and is driven by a single 48-MHz clock signal. With an oversampling ratio of only 24, the converter achieves a resolution of 91 dB, a peak SNR of 90 dB, and a peak SNDR of 85 dB at a Nyquist rate of 2 MHz after comb filtering. The power consumption of the converter is 230 mW, from a single 5-V supply voltage

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:33 ,  Issue: 7 )