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R, G, B acquisition interface with line-locked clock generator for flat panel display

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2 Author(s)
Marie, H. ; Philips Semicond., Caen, France ; Belin, P.

This paper presents the analysis, design, and experimental results of a triple 8-bit, 80 Msamples/s analog-to-digital acquisition channel with gain and clamp controls, together with a sample clock regenerator. While today's liquid crystal display (LCD) driver systems require some ten analog integrated circuits, this single chip offers three 7.4 effective bit 300 MHz bandwidth acquisition channels, sampled by a 250 ps rms long-term jitter regenerated clock. This new level of integration and performances is reached through the implementation of a new clock regenerator architecture. The integrated circuit, available in a 100-pin plastic package, is realized in a 13 GHz, 1 μm BiCMOS process and measures 25 mm2. It dissipates 1 W from 5 V supplies

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:33 ,  Issue: 7 )