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A compact neural network for partial-response maximum-likelihood detectors: algorithmic study

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3 Author(s)
Chou, E.Y. ; Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA ; Sheu, B.J. ; Wang, M.Y.

A compact neural network algorithm for partial-response maximum-likelihood (PRML) sequence detection is presented. Compact neural networks are a class of locally connected neural networks suitable for very large scale integration (VLSI) implementation. The hardware complexity for VLSI implementation of the proposed algorithm grows linearly with the level of the deliberately designed symbol interference effects of the partial-response (PR) signalling scheme. Large dedicated memory for storage of likelihood matrices in digital Viterbi-algorithm-based detectors is not needed for the proposed detector. Detailed analysis on network stability for network topology and time constant of an analog neuron is described. This detector algorithm has competitive bit-error rate performance when compared with the digital Viterbi algorithm under the noise condition for many real-world applications. The proposed algorithm is suitable for analog VLSI implementation because of its low time complexity and linear area complexity for the detection of PRML signalling schemes

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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on  (Volume:45 ,  Issue: 7 )