By Topic

Processor implementation for pipeline sparse matrix algorithm

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Kacarska, M. ; Elektrotehnicki Fakultet, Sv. Kiril i Metodij Univ., Skopje, Macedonia ; Andonov, D. ; Grnarov, A.

Efficient algorithms for engineering problems can be achieved by a combination of various optimization techniques. This paper presents an application of such combined approach for engineering problems involving large sparse matrices, using the example of digital filter analysis. The processor implementation of a pipeline sparse matrix algorithm demonstrates the optimization results achieved by: efficient modeling of a sequential algorithm, algorithm parallelization, parallel architecture process mapping, high processor utilization, specific processor hardware modeling and hardware optimization. First, the Crout's sequential algorithm for sparse matrix solution is modified and optimized into the CR algorithm. The two major processes LUP and REP are identified and parallelized. An algorithm for optimal pipeline mapping and module distribution is developed to achieve balanced processor load and high efficiency. The LUP and REP process computation structures are generalized in order to enable efficient processor implementation, optimizing processor hardware and program length

Published in:

Electrotechnical Conference, 1998. MELECON 98., 9th Mediterranean  (Volume:2 )

Date of Conference:

18-20 May 1998