Processor implementation for pipeline sparse matrix algorithm

Efficient algorithms for engineering problems can be achieved by a combination of various optimization techniques. This paper presents an application of such combined approach for engineering problems involving large sparse matrices, using the example of digital filter analysis. The processor implementation of a pipeline sparse matrix algorithm demonstrates the optimization results achieved by: efficient modeling of a sequential algorithm, algorithm parallelization, parallel architecture process mapping, high processor utilization, specific processor hardware modeling and hardware optimization. First, the Crout's sequential algorithm for sparse matrix solution is modified and optimized into the CR algorithm. The two major processes LUP and REP are identified and parallelized. An algorithm for optimal pipeline mapping and module distribution is developed to achieve balanced processor load and high efficiency. The LUP and REP process computation structures are generalized in order to enable efficient processor implementation, optimizing processor hardware and program length.