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Characterization of bipolar snapback and breakdown voltage in thin-film SOI transistors by two-dimensional simulation

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3 Author(s)
G. A. Armstrong ; Dept. of Electr. & Electron. Eng., Queen's Univ., Belfast, UK ; J. R. Davis ; A. Doyle

A two-dimensional finite-difference simulator for silicon-on-insulator (SOI) MOSFETs is presented. The simulator is derived from the MINIMOS4 simulator and incorporates additional features which permit the characterization of the bipolar snapback effect, which has been observed as a limiting feature in ultra-thin-film transistors. The snapback effect is illustrated as a hysteresis mechanism whereby, for a given bias condition, there are two different solutions to the semiconductor equations, depending on the starting condition. Examples of the application of the simulator to predict breakdown voltage in submicrometer devices are considered. Excellent agreement with measured values of breakdown voltage has been achieved for submicrometer n-channel transistors, both with and without the use of lightly doped drains

Published in:

IEEE Transactions on Electron Devices  (Volume:38 ,  Issue: 2 )