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Process limitation and device design tradeoffs of self-aligned TiSi 2 junction formation in submicrometer CMOS devices

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7 Author(s)

Submicrometer CMOS transistors require shallow junctions to minimize punchthrough and short-channel effects. Salicide technology is a very attractive metallization scheme to solve many CMOS scaling problems. However, to achieve a shallow junction with a salicide structure requires careful optimization for device design tradeoffs. Several proposed techniques to form shallow titanium silicide junctions are critically examined. Boron, BF2, arsenic, and phosphorus dopants were used to study the process parameters for low-leakage TiSi 2 p+/n and n+/p junctions in submicrometer CMOS applications. It is concluded that the dopant drive-out (DDO) from the TiSi2 layer to form a shallow junction scheme is not an efficient method for titanium salicide structure; poor device performance and unacceptably leaky junctions are obtained by this scheme. The conventional post junction salicide (PJS) scheme can produce shallow n+/p and p+/n junctions with junction depths of 0.12 to 0.20 μm below the TiSi2. Deep submicrometer CMOS devices with channel length of 0.40 to 0.45 μm can be fabricated with such junctions

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Electron Devices, IEEE Transactions on  (Volume:38 ,  Issue: 2 )