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Pipelined arrays for modular multiplication

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1 Author(s)
L. Ciminiera ; Dipt. di Autom. e Inf., Politecnico di Torino, Italy

New arrays performing the modular multiplication are presented; they operate on a bit-serial basis for both inputs and outputs. The distinctive characteristic of the arrays presented is the possibility to start a new operation, as soon as the cells in the array are no longer used for the previous one, thus allowing bit-level pipelining of the different multiplications. A first array presented has a short clock cycle and long latency, so that it is more suited for applications dealing with long blocks of data to be processed. A second one has a longer clock cycle and shorter latency, and it is more suited for repeated operation on the same block of data

Published in:

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on  (Volume:4 )

Date of Conference:

31 May-3 Jun 1998