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A low voltage design technique for low noise RF integrated circuits

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2 Author(s)
Abou-Allam, E. ; Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada ; Manku, T.

Analysis and optimization of the bias conditions and noise parameters of MOS devices are presented. A design technique based on a narrowband LC-folded cascode topology is proposed for low voltage RF integrated circuits. The technique is applied to the design of a 1 V LNA operating at 1.9 GHz using a 0.5 μm CMOS technology. Simulation results show that the LNA provide a noise figure of 1.7 dB, gain of 10 dB, and is well matched at the input. The LNA also provides a minimum noise figure of 1.6 dB

Published in:

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on  (Volume:4 )

Date of Conference:

31 May-3 Jun 1998

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