We are currently experiencing intermittent issues impacting performance. We apologize for the inconvenience.
By Topic

A low-cost architecture design with efficient data arrangement and memory configuration for MPEG-2 audio decoder

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Tsung-Han Tsai ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Liang-Gee Chen ; Sheng-Chieh Huang ; Hao-Chieh Chang

The paper describes a low-cost MPEG-2 audio decoder with a modified fast algorithm for decoding. In the modified decoding scheme, the computation amount of the bottleneck module can be reduced into one-forths of the original one. Also, the major memory storage only requires half size of the standard synthesis subband filterbank. The decoder is developed for the approaches of simplicity and low-cost architecture design, with the techniques of intelligent data arrangement and memory configuration

Published in:

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on  (Volume:4 )

Date of Conference:

31 May-3 Jun 1998