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A low-cost architecture design with efficient data arrangement and memory configuration for MPEG-2 audio decoder

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4 Author(s)
Tsung-Han Tsai ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Liang-Gee Chen ; Sheng-Chieh Huang ; Hao-Chieh Chang

The paper describes a low-cost MPEG-2 audio decoder with a modified fast algorithm for decoding. In the modified decoding scheme, the computation amount of the bottleneck module can be reduced into one-forths of the original one. Also, the major memory storage only requires half size of the standard synthesis subband filterbank. The decoder is developed for the approaches of simplicity and low-cost architecture design, with the techniques of intelligent data arrangement and memory configuration

Published in:

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on  (Volume:4 )

Date of Conference:

31 May-3 Jun 1998