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Low power 2D DCT chip design for wireless multimedia terminals

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5 Author(s)
Liang-Gee Chen ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Juing-Ying Jiu ; Hao-Chieh Chang ; Yung-Pin Lee
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In this paper, a low power 2-D DCT architecture based on direct 2-D approach is proposed. The direct 2-D consideration reduces computational complexity. According to this algorithm, a parallel distributed arithmetic (DA) architecture at reduced supply voltage is derived. In the real circuit implementation of the chip, an adder of low power consumption is designed, as well as a power-saving ROM and a low voltage two-port SRAM with sequential access. The resultant 2-D DCT chip is realized by 0.6 μm single-poly double-metal technology. Critical path simulation indicates a maximum input rate of 133 MHz, and it consumes 138 mW at 100 MHz

Published in:

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on  (Volume:4 )

Date of Conference:

31 May-3 Jun 1998