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Simultaneous switching noise analysis and low bouncing buffer design [CMOS ICs]

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3 Author(s)
Shyh-Jye Jou, ; Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan ; Wei-Chung Cheng ; Yu-Tao Lin

An accurate equation to estimate Simultaneous Switching Noise (SSN) in CMOS integrated circuits including the carrier velocity saturation effects of the short-channel MOSFET is proposed. Simulation results show that the proposed close-form equation estimates the SSN precisely and the error is below 5% as compared with HSPICE simulation results. Design procedures of low bouncing tapered buffer that take SSN into consideration are also proposed. Finally, several output buffer design examples are implemented to verify the low bouncing buffer design

Published in:

Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998

Date of Conference:

11-14 May 1998