By Topic

Design and implementation of high performance dynamic 64-bit parallel adder with enhanced testability

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Hwang, W. ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; Gristede, G.D. ; Sanda, P.N. ; Wang, S.Y.
more authors

This paper presents a fast, low power, binary carry look-ahead 64-bit dynamic parallel adder architecture for a high frequency microprocessor. The adder core is composed of several basic building blocks and feedback reset chain blocks implemented in self-resetting CMOS (SRCMOS) circuits. All circuits are design with enhanced testability. A new tool, SPA (SRCMOS Pulse Analyzer) is developed for dynamic and static checks. The nominal propagation delay and power dissipation of the adder are measured to be 1.5 ns (at 22 C with Vdd=2.5 V) and 300 mW. The adder core size is 1.6 mm×0.275 mm. The process that the design is based upon in a 0.5 μm IBM CMOS5X technology with 0.25 μm effective channel length and 5 layers of metal. The circuit techniques are ready to be migrated to sub-nanosecond microprocessor design

Published in:

Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998

Date of Conference:

11-14 May 1998