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A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme

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10 Author(s)
M. Hamada ; Syst. ULSI Eng. Lab., Toshiba Corp., Kawasaki, Japan ; M. Takahashi ; H. Arakida ; A. Chiba
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A novel design technique which combines a variable supply-voltage scheme and a clustered voltage scaling is presented (VS-CVS scheme). A theory to choose the optimum supply voltages in the VS-CVS scheme is discussed which enables us to perform chip design in a top-down fashion. Level-shifting flip-flops are developed which reduce power, delay and area penalties significantly. Application of this technique to an MPEG4 video codec saves 55% of the power dissipation without degrading circuit performance compared to a conventional CMOS design

Published in:

Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998

Date of Conference:

11-14 May 1998