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Design and analysis of a ±1 V CMOS four-quadrant analogue multiplier

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2 Author(s)
Seng, Y.K. ; Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore ; Rofail, S.S.

The design and analysis of a ±1 V CMOS four-quadrant analogue multiplier and a frequency doubler for low-voltage low-power applications are presented. The design is based on the current-mode approach and the square-law characteristics of an MOS transistor in saturation. The multiplier utilises I-V converters, a current mirror and four matched transistors to achieve a transresistance gain of 73 dBΩ, a -3 dB bandwidth of 4.3 MHz, a total harmonic distortion below 1% and a maximum power dissipation of 130 μW. Design guidelines have been set to link the circuit performance, in terms of the gain, the input operating range, the fabrication area, and the device aspect ratios, to key device and technology parameters. The scope for further performance improvement using BiCMOS is also highlighted. The experimental results obtained from the chip were found to be in close agreement with the simulated results

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Circuits, Devices and Systems, IEE Proceedings -  (Volume:145 ,  Issue: 3 )