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A 10 bit 40 MHz ADC using 0.8 μm Bi-CMOS technology

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6 Author(s)
Tsugaru, K. ; Toshiba Corp., Kawasaki, Japan ; Sugimoto, Y. ; Noda, M. ; Iwai, H.
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A 10-bit analog-to-digital converter applicable to digital video equipment and using 0.8-μm BiCMOS technology is discussed. In order to reduce power dissipation and chip size, a two-step parallel type conversion scheme is utilized. The 10-bit resolution has been realized at a maximum conversion rate of 40 MHz, power dissipation of 700 mW, and chip size of 4.1×4.8-mm2. A scheme that transforms coarse reference voltages to fine ladder resistors using buffer amplifiers has been used. As the emitter follower circuit can be used for the buffer amplifier, a small settling time is obtained. A subranging architecture has been adopted in which the full-scale range of fine ADC is consistent with the equivalent voltage to 1.5 LSB for coarse ADC. With this architecture, 10 bit resolution is not required for coarse ADC, and total resolution is decided by fine ADC

Published in:

Bipolar Circuits and Technology Meeting, 1989., Proceedings of the 1989

Date of Conference:

18-19 Sep 1989