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Semi-recursive VLSI architecture for two dimensional discrete wavelet transform

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3 Author(s)
Seung-Kwon Paek ; Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea ; Hyun-Kyu Jeon ; Lee-Sup Kim

This paper presents an efficient two-dimensional discrete wavelet transform (2-D DWT) VLSI architecture which calculates the 2-D DWT for image processing in real-time. The proposed architecture, semi-recursive 2-D DWT VLSI architecture, has the minimum H/W cost of internal word length, data-bus utilization, scheduling control overhead and storage size. Compared with the conventional recursive 2-D DWT VLSI architecture, the size of multipliers and registers are reduced by 13% and 34% respectively. Furthermore, the semi-recursive 2-D DWT VLSI architecture exploits the lapped block processing and hence has the minimum transposition storage size and short latency

Published in:

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on  (Volume:5 )

Date of Conference:

31 May-3 Jun 1998