A VLSI architecture design with lower hardware cost and less memory for separable 2-D discrete wavelet transform

This paper presents an efficient architecture for 2-D image decomposition of discrete wavelet transform. Our design approach reduces the transpose storage size and hardware cost efficiently, based on the input data reuse methodology and fully parallel pipelined architecture. The main characteristics of this architecture include: (1) lower hardware cost; (2) smaller transpose storage size; (3) shorter latency; (4) suitable VLSI implementation. Finally, all components in our architecture are simulated based on the accuracy requirement and realized as a single chip physically. The chip area is about 7600*8400 um/sup 2/ and its working frequency is 25 MHz.