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An array processor architecture with parallel data cache for image rendering and compositing

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2 Author(s)
M. Berekovic ; Inst. fur Theor. Nachrichtentech. und Inf., Hannover Univ., Germany ; P. Pirsch

This paper proposes a new array architecture for MPEG-4 image compositing and 3D rendering. The emerging MPEG-4 standard for multimedia applications allows VRML-like script-based compositing of audio-visual scenes from multiple audio and visual objects. MPEG-4 supports both natural (video) and synthetic (3D) visual objects or a combination of both. Objects can be manipulated e.g. positioned, rotated, warped or duplicated by user interaction. A coprocessor architecture is presented, that works in parallel to an MPEG-4 video and audio-decoder and a floating-point geometry-processor. It performs computation and bandwidth intensive low-level tasks for image compositing and rasterization. The processor consists of a SIMD array of 16 identical DSPs to reach the required processing power for real-time image warping, alpha-blending, z-buffering and phong-shading. The processor has an object-oriented parallel cache architecture with 2D virtual address space (e.g. textures) that allows concurrent and conflict-free access to shared image data objects for all 16 DSPs

Published in:

Computer Graphics International, 1998. Proceedings

Date of Conference:

22-26 Jun 1998