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Low-temperature buffer AlInAs/GaInAs on InP HEMT technology for ultra-high-speed integrated circuits

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9 Author(s)
Brown, A.S. ; Hughes Res. Lab., Malibu, CA, USA ; Chou, C.S. ; Delaney, M.J. ; Hooper, C.E.
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A report is presented on the development of a planar low-temperature buffer AlInAs/GaInAs on InP high-electron-mobility transistor (HEMT) technology for use in digital and analog integrated circuits. This technology is attractive for circuit applications because of the high achievable f/sub T/ and f/sub max/, low output conductance and gate leakage current, and reduced susceptibility to backgating effects. Two alternative logic families-UFL and SCFL (source-couple FET logic)-were chosen for the realization of digital circuits. Measurements on the UFL ring oscillators exhibited a minimum gate delay of 13 ps with a power dissipation of 1.1 mW/gate at room temperature. The gate delay rose to 25 ps when the power dissipation increased to 3 mW/gate. This gate delay is expected to drop significantly with reductions in diode level-shift series resistance and improvements in transistor f/sub T/. The most complex SCFL circuit tested was a divide-by-eight counter. The SCFL circuits were configured as flip-flops in the divide-by-eight mode. The circuit operated at a maximum clock rate of 12.5 GHz.<>

Published in:

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1989. Technical Digest 1989., 11th Annual

Date of Conference:

22-25 Oct. 1989