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A highly manufacturable 0.25 /spl mu/m multiple-Vt dual gate oxide CMOS process for logic/embedded IC foundry technology

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34 Author(s)
Chang, M.H. ; Res. & Dev., Taiwan Semicond. Manuf. Co., Shin-Chu, Taiwan ; Ting, J.K. ; Shy, J.S. ; Chen, L.
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A multiple-Vt high performance, high density and highly manufacturable 0.25 μm CMOS technology with a shallow trench isolation process has been successfully developed. Five metal layers with oxide CMP planarization, etchback W plug for borderless contacts/vias, and fully stacked contact/vias were used. Dual gate oxide process (5 nm for 2.5 V core, and 7 nm for 3.3 V I/O or 13 nm for 5 V I/O) with low defect density, and low Vt (∼0.2 V) or native Vt (∼0 V) devices for low power and mixed-mode applications are all demonstrated in this technology.

Published in:

VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on

Date of Conference:

9-11 June 1998