Referenced Items are not available for this document.
This paper describes the architecture of a scalable shared buffer ATM switch and FPGA (field programmable gate array) implementation. The proposed ATM switch has a 2-D array of sub-memory blocks as a shared buffer. We can enlarge the buffer capacity by increasing the array size without any change of circuit. The prototype switch has been designed for a 4×4 ATM switch which has a shared buffer for 32 16-byte cells and implemented using FPGA to verify its function. The operating frequency of the designed test-bed is 40 MHz
Published in:
ATM, 1998. ICATM-98., 1998 1st IEEE International Conference on
Date of Conference: 22-24 Jun 1998
- Page(s):
- 247 - 251
- Meeting Date :
- 22 Jun 1998-24 Jun 1998
- Print ISBN:
- 0-7803-4982-2
- INSPEC Accession Number:
- 6154319
- Conference Location :
- Colmar
- Digital Object Identifier :
- 10.1109/ICATM.1998.688184
- Product Type:
- Conference Publications
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