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A sophisticated bit-by-bit verifying scheme for NAND EEPROMs

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5 Author(s)
Sakui, K. ; ULSI Device Eng. Lab., Toshiba Corp., Yokohama, Japan ; Kanda, K. ; Nakamura, H. ; Imamiya, K.
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A sophisticated bit-by-bit verifying scheme, which is able to realize a tight programmed threshold voltage distribution of 0.8 V, has been proposed for NAND EEPROMs. A new bit-by-bit verifying circuit is composed of a conventional sense amplifier and a dynamic latch circuit with only three transistors, increasing the chip size of the 64 Mbit NAND EEPROM less than 1%.

Published in:

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Date of Conference:

11-13 June 1998