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A coding scheme for field-powered RF IC tag systems

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5 Author(s)
Tanaka, S. ; Central Res. Lab., Hitachi Ltd., Tokyo, Japan ; Ishifuji, T. ; Saito, T. ; Shida, M.
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This paper describes a new coding scheme and its CMOS implementation for field powered RF IC tag systems. The main feature of the new scheme is that it does not require a PLL for clock recovery and the decoding process, and the coding signal produced has 50% duty cycle and contains both clock and data. Also the clock signal generated by the decoder adopting the scheme drives the circuit at the proper time to achieve maximal power efficiency. A test chip has been fabricated with a 0.8 /spl mu/m standard CMOS process. The evaluation test board with this chip operates with 1 mW RF signals and no battery.

Published in:

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Date of Conference:

11-13 June 1998