By Topic

A jitter and data duty distortion tolerated PLL circuit for 156-Mbps burst-mode transmission

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
Sato, M. ; NEC Telecom Syst. Ltd., Kanagawa, Japan ; Aoki, Y. ; Baba, M. ; Wakayama, Y.
more authors

A new PLL circuit for 156-Mbps burst-mode transmission application in a passive optical network (PON) is described in this paper. For data recognition accuracy and jitter tolerance, we propose an ADR (adaptive data recognition) circuit using rising and falling phase average values extracted from input burst-mode data, and an EPA (edge phase averaging) circuit averaging rising and falling edge phases of input burst-mode data. The PLL circuit has been implemented on 3.3 V, 0.35 /spl mu/m CMOS standard cell, and has shown good system performance, such as a power penalty of less than 0.1 dB at 10/sup -8/ error rate.

Published in:

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Date of Conference:

11-13 June 1998